As on chip transistor density increases according to Moore's Law, a capability to design reliable multi-core processors operating with abundant parallelism is increasing as well. Indeed, modern multi-core architectures integrate many homogeneous simple cores on a same die, which favors exploitation of Thread Level Parallelism (TLP). However, while TLP may be exploited, many applications operating on a typical multi-core processor have a significant amount of sequential code fragments. Amdahl's Law states such applications suffer from poor speedup while operating on a multi-core processor because the sequential code fragments cannot exploit Instruction Level Parallelism (ILP) among the cores of the multi-core processor.
To solve the above problem certain adaptive multi-core architectures such as those disclosed in Mihai Pricopi and Tulika Mitra. Bahurupi: A Polymorphic Heterogeneous Multi-core Architecture. ACM TACO, 8(4):22:1-22:21, 2012; Engin Ipek et al. Core Fusion: Accommodating Software Diversity in Chip Multiprocessors. ISCA, pages 186-197, 2007; David Tarjan et al. Federation: Repurposing Scalar Cores for Out-of-order Instruction Issue. DAC, pages 772-775, 2008; and Changkyu Kim et al. Composable Lightweight Processors. MICRO, pages 381-394, 2007, have been proposed to solve the above mentioned limitations of simple cores. In general, the multi-core architectures discussed in the cited documents create virtual complex cores out of simple cores, where the virtual complex cores are capable of accelerating sequential fragments of the applications being executed by the multi-core processor by exploiting ILP. These adaptive multi-core processors offer far better performance compared to both classic homogeneous multi-cores and asymmetric multi-cores when a mixture of sequential and parallel applications co-exist in a processors workload.
The proposed adaptive multi-core processor designs discussed in the above cited documents primarily focus on an internal micro-architecture of the processor, a compiler for the processor, and a programming model. Consequently, the described multi-core processor designs ignore or make a simplifying assumption regarding a memory hierarchy for the multi-core processor. For instance, a common assumption in the above cited documents is that a first level data instruction cache must support reconfigurability. However, none of the above cited documents provides a solution to the need for reconfigurable cache architecture for adaptive multi-core processors.